Application specific integrated circuit (ASIC) technology has undergone rapid changes in recent years. Current ASIC chips may include functional blocks, such as microprocessors, interfaces, memory arrays, and DSPs (digital signal processors) all of which need to be validated for designs and tested for manufacturing defects.
Microprocessor testing is typically considered one of the most complex problems in ASIC testing, whether the microprocessor happens to be an ASIC core or a stand-alone device. This is because modern microprocessors are highly complex and typically enhanced with additional operating modes and features. For example, newer x86 microprocessors such as Pentium® processors as marketed by Intel® Corporation are designed to maintain software compatibility with previous 80x86 microprocessor generations (e.g., 8086/8, 80286, 80386, and 80486). These newer x86 microprocessors include multiple operating modes and are equipped with cache memory systems and added hardware support features for operation in multi-processor environments. Errors in the designs of microprocessors and defects introduced during manufacturing may cause the microprocessors to produce incorrect results during operation.
Traditionally functional tests have been used to ensure that complex devices such as microprocessors under test produce correct results in all possible operating environments. Functional tests are manually written by software designers/programmers or are generated by random instruction test (RIT) tools as described, for example, in the “Native Mode Functional Test Generation For Processors With Applications To Self Test and Design Validation” by Jian Shen and Jacobs A. Abraham of the Computer Engineering Research Center, University of Texas, IEEE International Test Conference, pp. 990-999, August 1998. In general, these functional tests include software instructions which cause a microprocessor under test to perform a desired activity and to produce a test result. The test result is compared with an expected test result derived from a functional specification of the microprocessor under test. Any difference between the test result produced by the microprocessor under test and the expected test result represents a failure of the functional test. Such a functional test failure may indicate improper microprocessor operation due to a design error or a manufacturing defect.
However, manual development of functional tests is very costly in terms of the (human) resources needed. Likewise, RIT tests are not very efficient in terms of high fault coverage and, often, require higher test data volume. Moreover, functional tests are performed by automatic test equipments (ATE) such as IC testers which require expensive, high performance pattern memory sub-systems to deliver complex test patterns. Since complex devices such as microprocessors have dramatically improved their performance, such as operating speeds, density, functionality, and pin counts, an IC tester for testing such microprocessors needs to be very large scale, high speed, and accordingly very expensive. For example, such an IC tester has several hundreds or more test pins (test channels), each of which includes a pattern generator, a timing generator and a frame processor, resulting in a very large and high cost system.
Due to high equipment costs and test generation costs inherent to functional tests, the semiconductor industry has adopted various design-for-test (DFT) techniques and built-in self-test (BIST) schemes such as scan, partial scan, logic BIST, scan-based BIST to structurally test various logic blocks within a microprocessor, via low cost IC testers. The main problem in these structural test approaches is the requirement of large amount of test data and additional hardware area (extra logic circuits) to implement the test logic. In addition, these test schemes also cause a 5-10% performance penalty. Typically, such a performance penalty is a signal propagation delay in the microprocessor because of the additional hardware overhead in the microprocessor. Thus, the design-for-test and built-in self-test schemes may adversely affect the microprocessor's performance, such as an operating speed because of the signal propagation delays. In addition, the collateral coverage from application of structural tests may be more limited compared to that achieved through the application of functional patterns.
Therefore there is need to develop test techniques that (a) enable automated random test generation in real time (b) are functional test based (c) can be applied on low cost structural testers and (d) are inexpensive to implement in silicon and (e) achieve high collateral coverage with at-speed test application, thus avoiding delay defect screening issues.